Embodiments of the present invention relate to a level converter circuit. Further embodiments relate to an input circuit with input transistors and a level converter circuit coupled to the input transistors. Further embodiments relate to a method for operating a level converter circuit. Some embodiments relate to a level converter for fast CMOS input circuits.
For realizing fast data transmission (of e.g. more than 1000 Mbit per second) across lossy cables, increased transmission power is necessitated. However, modern CMOS technologies have the limitation that fast transistors (having a structural size of less than 90 nm) have a lower dielectric strength. This is in particular critical for receiver circuits since here level conversion has to be performed, which can, at high signal levels (of e.g. more than 1V), no longer be realized with fast transistors.
Two solutions for solving this problem are known. According to a first solution, high input voltages are completely avoided, such that fast transistors can be used. This results, however, in a reduction of the transmission power or severely restricts the wirings that would otherwise be possible. According to a second solution, voltage-proof, slower transistors that perform a suitable level conversion are used for the input stage. However, this restricts the maximum data rate.
Due to the low switching velocity of these transistors, the usage of voltage-proof transistors results in an input stage with low amplification and bandwidth. On the one hand, this distorts the signal further, such that more measures for bandwidth compensation have to be taken, on the other hand, low amplification results in a poorer signal-to-noise ratio, since more amplifier stages are necessitated and more noise is added at lower signal levels.